Harry W. Peterson

Harry Peterson

4281 Orangewood Court

Concord, CA 94521

cell: (408) 455-4748

hpeterson@yanntek.com

Highly experienced, Caltech educated chip designer. Former Director of Design Engineering for Toshiba and Fellow of Video Technology for Pixelworks. 
Current practice mainly involves:

• Design and manufacture of high performance data converter circuits
• Optoelectronic devices, circuits, packages and systems
• RF Integrated circuits and wireless, wired and fiber-optic communications
• Development of display chips and systems for medical and consumer systems
• Telecommunications reliability, security, efficiency and analytics
• IP protection (strategy, patent portfolio acquisition, sale and defense)
• Litigation Support/Expert witness

Summary of Experience

2009-Present     Consultant, Yanntek Inc, Silicon Valley, CA
Primary activity:  Design

• Use behavioral simulation (e. g. Matlab) to map back-of-envelope concept sketches to rigorous design specifications that can efficiently guide system and circuit implementation.
• Design, simulate and verify devices, circuits, packages and systems.
• Support verification, manufacturability analysis, layout, new-product-bring-up and market-ramp activity.

Here are some of the circuits and systems I have recently designed:

• 14b Sigma-delta (ΣΔ ) ADC and 12b DAC for highly integrated wideband (terabit per second) fiber optic communications system. Process:  B55 (ST SiGe 55nm BiCMOS)

• Extreme-low-jitter clock distribution system for network chip
  Developed custom CML blocks for a single-chip network switch that features dozens of PCIe gen3 IO's with extremely tight timing requirement. Process:  TSMC 28HPC
  
  
• Timing and calibration circuits for a 5Gbps 12b analog-to-digital converter (interleaved SAR), with extreme-low-jitter clock distribution system and calibration circuitry. Process:  Global Foundries 65nm

Secondary activity:  Advise

Provide support expertise as follows:  

• Train design teams in the art of high performance mixed-signal chip simulation and verification
• Drive system-level hardware/software/application integration
• Support of outsourcing and design reviews
• Model-driven analytics and security
• Due-diligence in support of merger and acquisition (M&A) and investment activity
• Expert witness testimony

2009-2013         Board Proxy, Evatronix SA — Warsaw, Poland

Evatronix was an IC design startup launched shortly after Poland regained independence in 1989.  My role was to define and implement a high-growth strategy and to achieve a very successful exit.  I helped recruit and build two teams of analog designers (Warsaw and Gliwice), supervised and worked alongside them during the first four projects, delivered IP blocks to customers and assisted with bring-up of production chips.  Helped negotiate corporate exit (Cadence acquired Evatronix in 2013). 

2005-2009            Fellow and Senior Director of Engineering, Pixelworks (Nasdaq: PXLW) — San Jose, CA

Developed hardware and firmware systems used in consumer video products.  Optimized performance for 3D and super-resolution applications.  Introduced innovative low-cost packages.  Built and ramped video-chip design and support teams in Shanghai, San Jose, Portland and Toronto.   Led design of complex video chip (PEARL) and helped achieve market wins at Sony, Epson and other companies. Managed NPI (new-product-introduction) activities with foundries and package vendors. Participated in standards development groups (USB3 and VESA).  Helped map and execute corporate video-standards strategy (H.264, H.265, DisplayPort). 

My principle role during this period was to build a world-class design team in Shanghai, manage an existing portfolio and supervise porting to new processes and applications.  We developed data converters, video processing subsystems, and highly integrated, cost-effective SOCs.  I also recruited and supervised external contractors who supported our design and development activity.

2003-2005            Director of Design Engineering, Toshiba — San Jose, CA

Managed design and NPI (New Product Introduction) of a family of multi-standard >6Gbps SERDES phy's developed jointly with Rambus.  Led the Toshiba North America FAE team for chips and packages.  Supervised internal and external design activity for USB, XAUI, Fiber-channel, DDR, PCIe and SATA IP.

Managed definition, acquisition, development and qualification of new IP blocks, and integration in chips. 

Publications since 2010

“Design Principles and Realization of Electro-Optical Circuit Boards,” SPIE Photonics West, 2013

“Communicating Basic Process Parameters and Criteria for Mixed-Signal and RF Processes,” article in GSA FORUM, March 2011

"Systematic approach to verification of a mixed signal IP — HSIC PHY case study," IEEE IP SOC 2010, Grenoble

Presentations

“Behavioral Modeling facilitates Chip-Package Co-design,” Cadence user conference (CDNLive!), 3 May 2011, Munich

"Low cost high-performance packages,” invited talk at Warsaw University of Technology Conference, April 2009, Warsaw

"EDA implications of advances in video chips," presented at Mentor Graphics Workshop, February 2007, Wilsonville

"Integrating Physical Test into the IC Studio Workflow", U2U CAD Conference, February 2007, Santa Clara

"Where submicron CMOS Meets Acoustic Holography," Caltech Conference, February 2005, Palo Alto

"A Flex architecture for systems with embedded, spatially-distributed sensors," Flexible Electronics Workshop, Max Planck Institute, June 2003, Leipzig

“Sandstorm: Embedded Electronics for Spatially Diverse Sensors,” IEEE Signal Processing Society SCV,
December 2003, Sunnyvale

"The Quest for Greater-than-100dB on-chip Isolation," IEEE Workshop, April 2002, San Jose

Education           

California Institute of Technology, Pasadena, CA.  BS Physics
NASA (Goddard)
Stockholm Observatory, Saltsjöbaden, Sweden.

U.S. Patents Granted or Pending

#4021786 Memory cell circuit and semiconductor structure therefore

#20110242305 Immersive Multimedia Terminal

#2018157122 High Speed Wireless Data Network

#20180175180 Millimeter wave communication system

#20180248612 Millimeter wave communications through obstructions

#20180302238 High-speed wireless multi-path data network

Expert Witness/Litigation Support Experience

Testifying, writing expert witness reports, and presenting at Markman hearings